Pll( Phase-Locked Loop)
EEN 3096 Communication Electronics
Unlocked
Acquisition
Tracking(locked)
ABSTRACT We were assigned to build a phase locked loop frequency synthesiser. The purpose is to help students to gain experience in hardware construction, coordinated teamwork and project management. The design uses 74HC4046, a PLL integrated circuit (IC) made from CMOS technology A PLL is a closed loop frequency system that locks the phase of an output signal to an input reference signal. The term “lock” refers to a constant or zero phase difference between two signals. The signal from the feedback path, ffb, is compared to the input reference signal, f ref, until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. These components consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), and the voltage controlled oscillator (VCO). The PFD detects any phase differences in fref and ffb and then generates an error signal. A frequency synthesiser is a device that generates a large number of precise frequencies from a single reference frequency. Frequency synthesizer generates a frequency that can have a different frequency from the original reference signal. Frequency synthesisers are being included in many new communication system designs, because they are relatively inexpensive and can be controlled by digital circuitry. The design flow process included design and simulation of the components/system and it also included the VCO layout. The aim of this project is to design and construct PLL frequency synthesiser.
1|Page
EEN 3096 Communication Electronics ACKNOWLEDGEMENTS We would like to express our gratitude to all the people who gave us the chance to complete our report by providing help in various direct and indirect ways. Firstly we thank our lecturer, Dr Su Sandar Thwin, Mr Tiang Jun Jiat and Mr Aaras Y. Kraidi
Unlocked
Acquisition
Tracking(locked)
ABSTRACT We were assigned to build a phase locked loop frequency synthesiser. The purpose is to help students to gain experience in hardware construction, coordinated teamwork and project management. The design uses 74HC4046, a PLL integrated circuit (IC) made from CMOS technology A PLL is a closed loop frequency system that locks the phase of an output signal to an input reference signal. The term “lock” refers to a constant or zero phase difference between two signals. The signal from the feedback path, ffb, is compared to the input reference signal, f ref, until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. These components consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), and the voltage controlled oscillator (VCO). The PFD detects any phase differences in fref and ffb and then generates an error signal. A frequency synthesiser is a device that generates a large number of precise frequencies from a single reference frequency. Frequency synthesizer generates a frequency that can have a different frequency from the original reference signal. Frequency synthesisers are being included in many new communication system designs, because they are relatively inexpensive and can be controlled by digital circuitry. The design flow process included design and simulation of the components/system and it also included the VCO layout. The aim of this project is to design and construct PLL frequency synthesiser.
1|Page
EEN 3096 Communication Electronics ACKNOWLEDGEMENTS We would like to express our gratitude to all the people who gave us the chance to complete our report by providing help in various direct and indirect ways. Firstly we thank our lecturer, Dr Su Sandar Thwin, Mr Tiang Jun Jiat and Mr Aaras Y. Kraidi