Peripheral Component Interconnect (PCI)
Peripheral Component
Interconnect (PCI)
Babak Kia
Adjunct Professor
Boston University
College of Engineering
ENG SC757 - Advanced Microprocessor Design
Why PCI?
The original PC bus developed by IBM in 1982 was
16 bits wide and operated at 4.77 MHz
This was known as the ISA bus, capable of transferring data at a whopping rate of 9 Mbytes per second!
Gradually peripherals such as video cards and hard drives required a higher bandwidth, and in
1992 Intel introduced the PCI bus standard to allow connected devices direct access to the system memory
It detached the speed of the peripheral bus from that of the memory, so even though today’s Front
Side Buses can run up to 800 MHz, the PCI devices can operate at their own independent speed What is PCI?
The Peripheral Component Interconnect is an interconnect bus developed by Intel in 1992 which runs at 33 MHz and supports plug-and-play
It allows high speed connection between peripherals, and from the peripherals to the processor Allows for transfer of data amongst peripherals independently of the processor
Found on many desktops, but not limited to them, the PCI bus is a 32 bit wide bus capable of transferring at data rates up to 132 MBytes per second A 66 MHz, 64-bit version is capable of transfer rates of up to 524 Mbytes/second
1
PC System Architecture
Northbridge is the chipset which interfaces with memory, PCI bus, level 2 caches,
Accelerated Graphics
Port (AGP), on the
Front Side Bus (FSB)
Southbridge is the chipset which handles the basic I/O such as
USB, serial, audio,
IDE devices and ISA bus PC System Architecture
2
PCI Bus Signals
AD[31:0] – Multiplexed
Address/Data
C/BE[3:0]# - Command/Byte
Enable
• 0110: Memory Read
• 0111: Memory Write
PAR – Parity, always driven as even for all AD[31:0] and
C/BE[3:0] signals
PCLK – PCI Clock, operates from DC (0 Hz) to 33 MHz
RST# - Reset
PCI Bus Signals
FRAME# - Driven by bus
master
Interconnect (PCI)
Babak Kia
Adjunct Professor
Boston University
College of Engineering
ENG SC757 - Advanced Microprocessor Design
Why PCI?
The original PC bus developed by IBM in 1982 was
16 bits wide and operated at 4.77 MHz
This was known as the ISA bus, capable of transferring data at a whopping rate of 9 Mbytes per second!
Gradually peripherals such as video cards and hard drives required a higher bandwidth, and in
1992 Intel introduced the PCI bus standard to allow connected devices direct access to the system memory
It detached the speed of the peripheral bus from that of the memory, so even though today’s Front
Side Buses can run up to 800 MHz, the PCI devices can operate at their own independent speed What is PCI?
The Peripheral Component Interconnect is an interconnect bus developed by Intel in 1992 which runs at 33 MHz and supports plug-and-play
It allows high speed connection between peripherals, and from the peripherals to the processor Allows for transfer of data amongst peripherals independently of the processor
Found on many desktops, but not limited to them, the PCI bus is a 32 bit wide bus capable of transferring at data rates up to 132 MBytes per second A 66 MHz, 64-bit version is capable of transfer rates of up to 524 Mbytes/second
1
PC System Architecture
Northbridge is the chipset which interfaces with memory, PCI bus, level 2 caches,
Accelerated Graphics
Port (AGP), on the
Front Side Bus (FSB)
Southbridge is the chipset which handles the basic I/O such as
USB, serial, audio,
IDE devices and ISA bus PC System Architecture
2
PCI Bus Signals
AD[31:0] – Multiplexed
Address/Data
C/BE[3:0]# - Command/Byte
Enable
• 0110: Memory Read
• 0111: Memory Write
PAR – Parity, always driven as even for all AD[31:0] and
C/BE[3:0] signals
PCLK – PCI Clock, operates from DC (0 Hz) to 33 MHz
RST# - Reset
PCI Bus Signals
FRAME# - Driven by bus
master