Limitations of a Superscalar Architecture
LIMITATION OF SUPERSCALAR MICROPROCESSOR PERFORMANCE
By: - Akshita Banthia (11BCE0475)
Abstract
In today’s world there is a new form of microprocessor called superscalar. In this several instructions can be initiated simultaneously and executed independently during the same clock cycle. The limitation of this feature is the handling of data dependencies. If not handled effectively, execution rate of more than one instruction per cycle is difficult to achieve. This case study uses multi bit scoreboard architecture to handle data conflicts for out of order execution and completion of instructions. The paper analyses the performance of the superscalar microprocessor by using two stimulation models which uses benchmark programs and one calculation model which uses queuing networks to derive the formula for data deficiencies from the peak performance.
Introduction
The single bit scoreboard is sufficient to detect dependency in processors with only one pipeline and also stop the flow of instructions until the line is cleared. Whereas a multi bit scoreboard is used in processors with multiple instructions. In this the multiple bit scoreboard in combination with temporary result registers will maintain the flow of the instructions and also to achieve peak performance a branch prediction unit is included.
Multi bit scoreboard architecture
Model
In this model the pipeline architecture has been implemented and it consists of four stages instruction fetch, instruction decodes, execution, and write-back. Instructions are fetched from the external memory or the cache memory to the instruction buffers and then transferred into the decoding units. The set of temporary registers are used as renaming registers for instructions with output and anti-dependencies. The branch prediction unit predicts the next stream of instructions. Data needed by the load/store instructions is handled by the data cache. In case of an interrupt the retire unit restores the proper
By: - Akshita Banthia (11BCE0475)
Abstract
In today’s world there is a new form of microprocessor called superscalar. In this several instructions can be initiated simultaneously and executed independently during the same clock cycle. The limitation of this feature is the handling of data dependencies. If not handled effectively, execution rate of more than one instruction per cycle is difficult to achieve. This case study uses multi bit scoreboard architecture to handle data conflicts for out of order execution and completion of instructions. The paper analyses the performance of the superscalar microprocessor by using two stimulation models which uses benchmark programs and one calculation model which uses queuing networks to derive the formula for data deficiencies from the peak performance.
Introduction
The single bit scoreboard is sufficient to detect dependency in processors with only one pipeline and also stop the flow of instructions until the line is cleared. Whereas a multi bit scoreboard is used in processors with multiple instructions. In this the multiple bit scoreboard in combination with temporary result registers will maintain the flow of the instructions and also to achieve peak performance a branch prediction unit is included.
Multi bit scoreboard architecture
Model
In this model the pipeline architecture has been implemented and it consists of four stages instruction fetch, instruction decodes, execution, and write-back. Instructions are fetched from the external memory or the cache memory to the instruction buffers and then transferred into the decoding units. The set of temporary registers are used as renaming registers for instructions with output and anti-dependencies. The branch prediction unit predicts the next stream of instructions. Data needed by the load/store instructions is handled by the data cache. In case of an interrupt the retire unit restores the proper