Ece 585 Project 2 Spring 13 Ver1 Simulation of Cpu, Cache, Bus, and Memory Datapath
ECE 585 Project 2 Spring 13 ver1 Simulation of CPU, Cache, Bus, and Memory Datapath
1. INTRODUCTION Project 2 is due Thurs Apr 11 EOD. You may work as groups of up to two. Submit your report to the Project 2 folder in the Electronic Black Board for the course. NO OTHE FORM OF SUBMISSION OR LATE SUBMISSIONS WILL BE ACCEPTED. In this project, you will simulate a CPU, cache, bus, and memory complex for a set of instructions with emphasis on the cache operation. The overall block diagram is shown in Figure 1. Bus
Cache
Memory
CPU
Figure 1: Overall Block Diagram The goal of this project is to provide you with a more practical hands-on approach to computer architecture design problems. The processor complex you will be designing is a 32-bit version of the MIPS processor; however, the instruction set will be a small subset of the actual MIPS ISA. You should implement the end to end operation of the complex utilizing the VHDL hardware descriptive language. You may use any constructs within the VHDL language, however, the design must be of your own. Copying of any form from any other student or any internal or external sources is illegal and will not be accepted. The processor supports the three instruction formats: R-format, I-format, and J-format as described in the text book and lectures. Table I Summarizes the core set of instructions for your ISA. The memory is assumed to be byte addressable and each word is 32 bits.
Table I: Core MIPS Instruction Set to be Designed (with example) OpCode [31 : 26] 100011 101011 000000 000100 Function Field [5 : 0] --100000 -Instruction lw sw add beq (Custom set) Operation lw $s1, 200($t3) sw $s3, 100($t4) add $s3, $t3, $t2 beq $s5, $t6, 400
The total set you need to design is the core set as above + a custom set designated for you as follows. Student ID ending in: 1. BNE, LUI 2. NOR, SLL 3. ADDI, LUI 4. BNE, LUI 5. NOR, LUI 6. ANDI, JR 7. BNE, LUI 8. NOR, LUI 9. ANDI, JR 0. ADDI, LUI
2. Implementation Details
1. INTRODUCTION Project 2 is due Thurs Apr 11 EOD. You may work as groups of up to two. Submit your report to the Project 2 folder in the Electronic Black Board for the course. NO OTHE FORM OF SUBMISSION OR LATE SUBMISSIONS WILL BE ACCEPTED. In this project, you will simulate a CPU, cache, bus, and memory complex for a set of instructions with emphasis on the cache operation. The overall block diagram is shown in Figure 1. Bus
Cache
Memory
CPU
Figure 1: Overall Block Diagram The goal of this project is to provide you with a more practical hands-on approach to computer architecture design problems. The processor complex you will be designing is a 32-bit version of the MIPS processor; however, the instruction set will be a small subset of the actual MIPS ISA. You should implement the end to end operation of the complex utilizing the VHDL hardware descriptive language. You may use any constructs within the VHDL language, however, the design must be of your own. Copying of any form from any other student or any internal or external sources is illegal and will not be accepted. The processor supports the three instruction formats: R-format, I-format, and J-format as described in the text book and lectures. Table I Summarizes the core set of instructions for your ISA. The memory is assumed to be byte addressable and each word is 32 bits.
Table I: Core MIPS Instruction Set to be Designed (with example) OpCode [31 : 26] 100011 101011 000000 000100 Function Field [5 : 0] --100000 -Instruction lw sw add beq (Custom set) Operation lw $s1, 200($t3) sw $s3, 100($t4) add $s3, $t3, $t2 beq $s5, $t6, 400
The total set you need to design is the core set as above + a custom set designated for you as follows. Student ID ending in: 1. BNE, LUI 2. NOR, SLL 3. ADDI, LUI 4. BNE, LUI 5. NOR, LUI 6. ANDI, JR 7. BNE, LUI 8. NOR, LUI 9. ANDI, JR 0. ADDI, LUI
2. Implementation Details