Vlsi Whatsup
Lecture 0
VLSI Design
Introduction to the subject
Rajesh Ghongade VIIT
• Teaching Scheme
– Lectures: 3 Hrs/week – Practical: 2 Hrs/Week
• Examination Scheme
– Paper: 100 Marks – Practical: 50 Marks – Oral: 25 Marks
Unit-I
VHDL Modeling and Design Flow Introduction to VLSI: complete VLSI design flow (with reference to an EDA tool). Sequential, Data flow, and Structural Modeling. Functions. Procedures, attributes. Test benches, Synthesizable, and non synthesizable statements; packages and configurations Modeling in VHDL with examples of circuits such as counters, shift registers, bidirectional bus, etc.
Unit 2
FSM And Sequential Logic Principles Sequential Circuits, Meta-stability Synchronization, Design of Finite State Machines, and State minimization, FSM CASE STUDIES - Traffic Light control. Lift Control and UART STA and DTA
Unit 3
Programmable Logic Devices Introduction to the CPLDs, Study of architecture of CPLD. and Study of the Architecture of FPGA
Unit 4
System On Chip One, two phase clock, Clock distribution. Power distribution. Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing. Off chip connections, I/O Architectures, Wire parasitics, EMI immune design. Study of memory-Basics of memory includes types of memory cells and memory architectures. Types of memory, based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO.
Unit 5
CMOS VLSI CMOS parasitics, equivalent circuit, body effect, Technology Scaling, A. parameter. Detail study of Inverter Characteristics, power dissipation, power delay product, CMOS combinational logic design and W/L calculations. Transmission gates, Introduction to CMOS layout.
Unit 6
Testability Need of Design for testability, Introduction to Fault Coverage, Testability. Design- forTestability, Controllability and Observability, Stuck-at Fault Model. Stuck-Open and Stuck-Short faults. Boundary Scan check. JTAG technology;
VLSI Design
Introduction to the subject
Rajesh Ghongade VIIT
• Teaching Scheme
– Lectures: 3 Hrs/week – Practical: 2 Hrs/Week
• Examination Scheme
– Paper: 100 Marks – Practical: 50 Marks – Oral: 25 Marks
Unit-I
VHDL Modeling and Design Flow Introduction to VLSI: complete VLSI design flow (with reference to an EDA tool). Sequential, Data flow, and Structural Modeling. Functions. Procedures, attributes. Test benches, Synthesizable, and non synthesizable statements; packages and configurations Modeling in VHDL with examples of circuits such as counters, shift registers, bidirectional bus, etc.
Unit 2
FSM And Sequential Logic Principles Sequential Circuits, Meta-stability Synchronization, Design of Finite State Machines, and State minimization, FSM CASE STUDIES - Traffic Light control. Lift Control and UART STA and DTA
Unit 3
Programmable Logic Devices Introduction to the CPLDs, Study of architecture of CPLD. and Study of the Architecture of FPGA
Unit 4
System On Chip One, two phase clock, Clock distribution. Power distribution. Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing. Off chip connections, I/O Architectures, Wire parasitics, EMI immune design. Study of memory-Basics of memory includes types of memory cells and memory architectures. Types of memory, based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO.
Unit 5
CMOS VLSI CMOS parasitics, equivalent circuit, body effect, Technology Scaling, A. parameter. Detail study of Inverter Characteristics, power dissipation, power delay product, CMOS combinational logic design and W/L calculations. Transmission gates, Introduction to CMOS layout.
Unit 6
Testability Need of Design for testability, Introduction to Fault Coverage, Testability. Design- forTestability, Controllability and Observability, Stuck-at Fault Model. Stuck-Open and Stuck-Short faults. Boundary Scan check. JTAG technology;