Vedic Maths
ANALYSIS, VERIFICATION AND FPGA IMPLEMENTATION OF VEDIC MULTIPLIER WITH BIST CAPABILITY A thesis report submitted in the partial fulfillment of the requirement for the award of the degree of Master of Technology in VLSI Design & CAD Submitted by Vinay Kumar Roll No.: 60761026 Under the Guidance Of Mr. Arun Kumar Chatterjee Lecturer, ECED
Department of Electronics and Communication Engineering THAPAR UNIVERSITY (Formerly Known as Thapar Institute of Engineering and Technology) PATIALA-147004, INDIA June – 2009
DECLARATION
I hereby declare that the work which is being presented in the thesis entitled, “Analysis, Verification and FPGA Implementation of Vedic Multiplier with BIST Capability” in partial fulfillment of the requirement for the award of degree of M.Tech (VLSI Design & CAD) at electronics and Communication Department of Thapar University, Patiala, is an authentic record of my own work carried out under the supervision of Mr. Arun Kumar Chatterjee, Lecturer, ECED. The matter presented in this thesis has not been submitted in any other University/Institute for the award of my degree.
Date:
Vinay Kumar Roll.No. 60761026
It is certified that the above statement made by the student is correct to the best of my knowledge and belief.
Mr. Arun Kumar Chatterjee Lecturer ECED, Thapar University Patiala -147004
Countersigned by:
Dr. A. K. Chatterjee Professor & Head Electronics and Communication Engg. Department Thapar University, Patiala - 147004
Dr. R. K. Sharma Dean Academic Affairs Thapar University Patiala – 147004
i
ACKNOWLEDGEMENT
To discover, analyze and to present something new is to venture on an untrodden path towards and unexplored destination is an arduous adventure unless one gets a true torchbearer to show the way. I would have never succeeded in completing my task without the cooperation, encouragement and help provided to me by various people. Words are often too less to reveals one‟s deep regards. I take this
Department of Electronics and Communication Engineering THAPAR UNIVERSITY (Formerly Known as Thapar Institute of Engineering and Technology) PATIALA-147004, INDIA June – 2009
DECLARATION
I hereby declare that the work which is being presented in the thesis entitled, “Analysis, Verification and FPGA Implementation of Vedic Multiplier with BIST Capability” in partial fulfillment of the requirement for the award of degree of M.Tech (VLSI Design & CAD) at electronics and Communication Department of Thapar University, Patiala, is an authentic record of my own work carried out under the supervision of Mr. Arun Kumar Chatterjee, Lecturer, ECED. The matter presented in this thesis has not been submitted in any other University/Institute for the award of my degree.
Date:
Vinay Kumar Roll.No. 60761026
It is certified that the above statement made by the student is correct to the best of my knowledge and belief.
Mr. Arun Kumar Chatterjee Lecturer ECED, Thapar University Patiala -147004
Countersigned by:
Dr. A. K. Chatterjee Professor & Head Electronics and Communication Engg. Department Thapar University, Patiala - 147004
Dr. R. K. Sharma Dean Academic Affairs Thapar University Patiala – 147004
i
ACKNOWLEDGEMENT
To discover, analyze and to present something new is to venture on an untrodden path towards and unexplored destination is an arduous adventure unless one gets a true torchbearer to show the way. I would have never succeeded in completing my task without the cooperation, encouragement and help provided to me by various people. Words are often too less to reveals one‟s deep regards. I take this
References: [13] Himanshu Thapliyal and M.B Srinivas, “An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics”, IEEE, 2005. [14] [15] “Spartan-3E FPGA Starter Kit Board User Guide”, UG230 (v1.1) June 20, 2008