Uart
PART II
I/O MODULES
CHAPTER 7
UART
7.1
INTRODUCTION
Universal asynchronous receiver and transmitter (UART) is a circuit that sends parallel data through a serial line. UARTs are frequently used in conjunction with the EIA (Electronic Industries Alliance) RS-232 standard, which specifies the electrical, mechanical, functional, and procedural characteristics of two data communication equipment. Because the voltage level defined in RS-232 is different from that of FPGA I/O, a voltage converter chip is needed between a serial port and an FF’GA’s IiO pins. The S3 board has a RS-232 port with the standard nine-pin connector. The board contains the necessary voltage converter chip and configures the various RS-232’s control signals to automatically generate acknowledgment for the PC’s serial port. A standard straightthrough serial cable can be used to connect the S3 board and PC’s serial port. The S3 board basically handles the RS-232 standard and we only need to concentrate on the design of the UART circuit. A UART includes a transmitter and a receiver. The transmitter is essentially a special shift register that loads data in parallel and then shifts it out bit by bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then reassembles the data. The serial line is ’ 1’ when it is idle. The transmission starts with a start bit, which is ’O’, followed by data bits and an optional parity bit, and ends with stop bits, which are ’1’. The number of data bits can be 6,7, or 8. The optional parity bit is used for error detection. For odd parity, it is set to ’0’ when the data bits have an odd number of 1’s. For even parity, it is set to ’0’ when the data bits have an even number of 1’s. The number of stop bits can be 1, 1.5, or 2.
FPGA Prototyping by VHDL Examples. By Pong P. Chu Copyright @ 2008 John Wiley & Sons, Inc.
163
164
UART
4 G:i*:x x idle d2
d3
x
d4
d5
d6
1d7 y
stop bit
Figure 7 1
I/O MODULES
CHAPTER 7
UART
7.1
INTRODUCTION
Universal asynchronous receiver and transmitter (UART) is a circuit that sends parallel data through a serial line. UARTs are frequently used in conjunction with the EIA (Electronic Industries Alliance) RS-232 standard, which specifies the electrical, mechanical, functional, and procedural characteristics of two data communication equipment. Because the voltage level defined in RS-232 is different from that of FPGA I/O, a voltage converter chip is needed between a serial port and an FF’GA’s IiO pins. The S3 board has a RS-232 port with the standard nine-pin connector. The board contains the necessary voltage converter chip and configures the various RS-232’s control signals to automatically generate acknowledgment for the PC’s serial port. A standard straightthrough serial cable can be used to connect the S3 board and PC’s serial port. The S3 board basically handles the RS-232 standard and we only need to concentrate on the design of the UART circuit. A UART includes a transmitter and a receiver. The transmitter is essentially a special shift register that loads data in parallel and then shifts it out bit by bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then reassembles the data. The serial line is ’ 1’ when it is idle. The transmission starts with a start bit, which is ’O’, followed by data bits and an optional parity bit, and ends with stop bits, which are ’1’. The number of data bits can be 6,7, or 8. The optional parity bit is used for error detection. For odd parity, it is set to ’0’ when the data bits have an odd number of 1’s. For even parity, it is set to ’0’ when the data bits have an even number of 1’s. The number of stop bits can be 1, 1.5, or 2.
FPGA Prototyping by VHDL Examples. By Pong P. Chu Copyright @ 2008 John Wiley & Sons, Inc.
163
164
UART
4 G:i*:x x idle d2
d3
x
d4
d5
d6
1d7 y
stop bit
Figure 7 1