Thyristor Ram
THYRISTOR RAM
Muktesh Waghmare, Raman Gaikwad
1: Principle:
Thyristor is well-known for its high-current drive capability and its bi-stable characteristics. It has been widely used in power electronics applications. With the exponential advances in CMOS technology tiny thyristor devices can now be easily embedded into conventional nano-scale CMOS. This enables the creation of a memory cell technology with features that include small cell size, high performance, reliable device operation, and good scalability. Use of thyristor provides a positive regenerative feedback that results in very large bit cell operation margins. The difference is that the four-transistor CMOS latch of a 6T-SRAM is replaced by the PNP-NPN bipolar latch of a single thyristor device, which reduces cell area dramatically and enables high-density macros.
2: Need of the technology: There has always existed a fundamental performance-density trade-off between SRAM and DRAM, the only two commercially viable volatile memory technologies. SRAM provides high performance at the expense of a large cell area, while DRAM provides high density but with low performance. The internal latch of a SRAM cell comprises of four-six transistors. This degrades the packaging density of a SRAM based memory. The performance limitation of DRAM is primarily a result of using a passive capacitor as the storage device without an internal gain. DRAM read operation is therefore destructive and the data retention is highly leakage sensitive. Destructive read requires the use of a read and write-back operation for every memory access or refresh operation, slowing down the random cycle time. Since a T-RAM cell consists of only two elements (a thyristor device and an access FET), its cell area is significantly smaller than 6T SRAM. The slow turn-off speed of a conventional thyristor is addressed in a T-RAM cell through the use of a thyristor structure, called thin capacitively coupled thyristor TCCT).
3:
Muktesh Waghmare, Raman Gaikwad
1: Principle:
Thyristor is well-known for its high-current drive capability and its bi-stable characteristics. It has been widely used in power electronics applications. With the exponential advances in CMOS technology tiny thyristor devices can now be easily embedded into conventional nano-scale CMOS. This enables the creation of a memory cell technology with features that include small cell size, high performance, reliable device operation, and good scalability. Use of thyristor provides a positive regenerative feedback that results in very large bit cell operation margins. The difference is that the four-transistor CMOS latch of a 6T-SRAM is replaced by the PNP-NPN bipolar latch of a single thyristor device, which reduces cell area dramatically and enables high-density macros.
2: Need of the technology: There has always existed a fundamental performance-density trade-off between SRAM and DRAM, the only two commercially viable volatile memory technologies. SRAM provides high performance at the expense of a large cell area, while DRAM provides high density but with low performance. The internal latch of a SRAM cell comprises of four-six transistors. This degrades the packaging density of a SRAM based memory. The performance limitation of DRAM is primarily a result of using a passive capacitor as the storage device without an internal gain. DRAM read operation is therefore destructive and the data retention is highly leakage sensitive. Destructive read requires the use of a read and write-back operation for every memory access or refresh operation, slowing down the random cycle time. Since a T-RAM cell consists of only two elements (a thyristor device and an access FET), its cell area is significantly smaller than 6T SRAM. The slow turn-off speed of a conventional thyristor is addressed in a T-RAM cell through the use of a thyristor structure, called thin capacitively coupled thyristor TCCT).
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References: [1] http://www.t-ram.com/technology/Publications.html [2] http://www.t-ram.com/technology/documents/HotChips2007_TRAM.pdf [3] IEEE International conference “Optimization of Substrate Doping for Back-Gate Control in SOI T-RAM Memory Technology" [4]IEEE International Electron Device Conference (IEDM)"A novel capacitor-less DRAM Cell using Thin Capacitively-Coupled Thyristor (TCCT)" [5]IEEE International Electron Device Conference (IEDM) "Fully Planar 0.562μm2 T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High-Performance SRAMs"