Mcmm Vlsi
With designs becoming increasingly complex by the day and transistor geometries shrinking, almost all the functional domains across SoC design teams are having a hard time to signoff their functions and Static Timing Analysis (STA) timing closure is also no exception. STA Timing closure is always an important and critical part of SoC design and lower technology nodes have only compounded the challenges for STA teams.
As the VLSI industry has entered the epoch of a lower technology node, diminishing transistor sizes and interconnect lengths have disturbed the ratio of cell and interconnect delays. This leads to requirement of signing off the SoC at multiple corners. After timing signoff at multiple Processes, Voltage, Temperature (PVT) corners, the silicon fabricated at submicron technology nodes shows appreciable increase in yield in terms of meeting timing specifications of the design.
However, timing closure at multiple PVT corners is in itself a huge challenge for the physical design team. This article will discuss these challenges and touch upon methodologies available to overcome them. We will discuss in detail, our solution to reduce the number of optimization corners in order to achieve efficient and coherent timing closure in minimum time. But before this, let us discuss in brief, the need to have multiple PVT corners for timing signoff.
Cell delays and interconnect delays are governed by manufacturing Process (P), operating Voltage (V) and ambient Temperature (T) properties of dies. These factors determine the physical properties of cells and interconnect like W/L ratio of cells and Resistance (R) and Capacitance (C) value of interconnects. At the 180-nm technology node and above, timing signoff at worst and best standard cell PVT corners with 2 RC extraction corners, namely, Cmax Rmin (Cmax) , and Cmin Rmax ( Cmin) was sufficient. On similar lines at 90 nm node 2 additional process corners Best Hot (Best process, Voltage at max temperature) and
As the VLSI industry has entered the epoch of a lower technology node, diminishing transistor sizes and interconnect lengths have disturbed the ratio of cell and interconnect delays. This leads to requirement of signing off the SoC at multiple corners. After timing signoff at multiple Processes, Voltage, Temperature (PVT) corners, the silicon fabricated at submicron technology nodes shows appreciable increase in yield in terms of meeting timing specifications of the design.
However, timing closure at multiple PVT corners is in itself a huge challenge for the physical design team. This article will discuss these challenges and touch upon methodologies available to overcome them. We will discuss in detail, our solution to reduce the number of optimization corners in order to achieve efficient and coherent timing closure in minimum time. But before this, let us discuss in brief, the need to have multiple PVT corners for timing signoff.
Cell delays and interconnect delays are governed by manufacturing Process (P), operating Voltage (V) and ambient Temperature (T) properties of dies. These factors determine the physical properties of cells and interconnect like W/L ratio of cells and Resistance (R) and Capacitance (C) value of interconnects. At the 180-nm technology node and above, timing signoff at worst and best standard cell PVT corners with 2 RC extraction corners, namely, Cmax Rmin (Cmax) , and Cmin Rmax ( Cmin) was sufficient. On similar lines at 90 nm node 2 additional process corners Best Hot (Best process, Voltage at max temperature) and