Fpga Vhdl
10-11-2012
Hardware Description Language (HDL)
VHDL for Specification
FPGA
VHDL for Simulation
VHDL for Synthesis
2
Levels of design description
Register Transfer Level (RTL) Design Description
Algorithmic level Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level
Level of description most suitable for synthesis
FF
Combinational Logic
FF
Combinational Logic
…
Registers
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012
3
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012
4
VHDL Design Styles
VHDL Design Styles
World of Integrated Circuits
Integrated Circuits
• Testbenches
Full-Custom ASICs Semi-Custom ASICs
dataflow
structural
behavioral
User Programmable
Concurrent statements
Components and interconnects
Sequential statements • Registers, counters, etc. • State machines
PLD
FPGA
PAL Subset most suitable for synthesis
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012 5
PLA
PML
LUT
(Look-Up Table)
MUX
Gates
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012
6
1
10-11-2012
What is an FPGA?
• Field Programmable Gate Arrays • Field programmability is achieved through switches (Transistors are controlled by memory elements or fuses) • Switches control the following aspects
• Interconnection among wire segments • Configuration of logic blocks
Why FPGAs?
• By the early 1980’s most of the logic circuits in typical systems where absorbed by a handful of standard large scale integrated circuits (LSI).
• Microprocessors, bus/IO controllers, system timers,…..
• Every system still had the need for random “glue logic” to help connect the large ICs:
• generating global control signals (for resets etc.) • data formatting (serial to parallel, multiplexing, etc.)
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012 7 EC3034 Modeling and Testing of
Hardware Description Language (HDL)
VHDL for Specification
FPGA
VHDL for Simulation
VHDL for Synthesis
2
Levels of design description
Register Transfer Level (RTL) Design Description
Algorithmic level Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level
Level of description most suitable for synthesis
FF
Combinational Logic
FF
Combinational Logic
…
Registers
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012
3
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012
4
VHDL Design Styles
VHDL Design Styles
World of Integrated Circuits
Integrated Circuits
• Testbenches
Full-Custom ASICs Semi-Custom ASICs
dataflow
structural
behavioral
User Programmable
Concurrent statements
Components and interconnects
Sequential statements • Registers, counters, etc. • State machines
PLD
FPGA
PAL Subset most suitable for synthesis
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012 5
PLA
PML
LUT
(Look-Up Table)
MUX
Gates
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012
6
1
10-11-2012
What is an FPGA?
• Field Programmable Gate Arrays • Field programmability is achieved through switches (Transistors are controlled by memory elements or fuses) • Switches control the following aspects
• Interconnection among wire segments • Configuration of logic blocks
Why FPGAs?
• By the early 1980’s most of the logic circuits in typical systems where absorbed by a handful of standard large scale integrated circuits (LSI).
• Microprocessors, bus/IO controllers, system timers,…..
• Every system still had the need for random “glue logic” to help connect the large ICs:
• generating global control signals (for resets etc.) • data formatting (serial to parallel, multiplexing, etc.)
EC3034 Modeling and Testing of Digital Systems – Monsoon 2012 7 EC3034 Modeling and Testing of