Domino Logic
1
Domino Logic
Kapalavayi Sai Ram, (2012EE10455), Electrical
Engineering
Abstract—Dynamic logic circuits are of great use in modern digital VLSI circuits. Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. Domino logic circuits, one well known dynamic logic family, which, however, suffers from its inability to perform inversions. Various methods have been proposed to overcome this restriction. One such method is realization of the circuit which requires the implementation of inverted logic using mixed static and domino logic. Implementation of inverted logic using mixed static and domino logic is discussed in this paper along with other advantages and disadvantages of domino logic over static CMOS logic.
Index Terms—Dynamic Logic, Domino Logic, Mixed CMOS,
Pull Down Network (PDN), Pull Up Network (PUP), Static
Logic
I. INTRODUCTION
Though static CMOS logic is greatly used in digital VLSI implementations, it has got its own drawbacks. Advantages of static CMOS gates:
•
Easier conversion from logic to fets.
•
Rail to rail switching
•
Very low static power dissipation
Disadvantages of static CMOS gates:
•
For every input we need one pfet and one nfet.
•
Larger circuit area due to pfets
•
High Capacitive loading
•
Pfets are relatively slow when compare to nfets. Majority of the problems are due to pull up network in the
CMOS implementation. So we can replace that pseudo-NMOS load (pfet with grounded gate). By doing this we are reducing the static power consumption but there are still some problems:
•
It dissipates static power even when output is low •
Output rise time increases
These problems are solved using dynamic logic instead of static logic. Dynamic logic uses a clock signal in its implementation in combinational circuits. Dynamic logic circcuits are much faster than static logic implementations and
Domino Logic
Kapalavayi Sai Ram, (2012EE10455), Electrical
Engineering
Abstract—Dynamic logic circuits are of great use in modern digital VLSI circuits. Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. Domino logic circuits, one well known dynamic logic family, which, however, suffers from its inability to perform inversions. Various methods have been proposed to overcome this restriction. One such method is realization of the circuit which requires the implementation of inverted logic using mixed static and domino logic. Implementation of inverted logic using mixed static and domino logic is discussed in this paper along with other advantages and disadvantages of domino logic over static CMOS logic.
Index Terms—Dynamic Logic, Domino Logic, Mixed CMOS,
Pull Down Network (PDN), Pull Up Network (PUP), Static
Logic
I. INTRODUCTION
Though static CMOS logic is greatly used in digital VLSI implementations, it has got its own drawbacks. Advantages of static CMOS gates:
•
Easier conversion from logic to fets.
•
Rail to rail switching
•
Very low static power dissipation
Disadvantages of static CMOS gates:
•
For every input we need one pfet and one nfet.
•
Larger circuit area due to pfets
•
High Capacitive loading
•
Pfets are relatively slow when compare to nfets. Majority of the problems are due to pull up network in the
CMOS implementation. So we can replace that pseudo-NMOS load (pfet with grounded gate). By doing this we are reducing the static power consumption but there are still some problems:
•
It dissipates static power even when output is low •
Output rise time increases
These problems are solved using dynamic logic instead of static logic. Dynamic logic uses a clock signal in its implementation in combinational circuits. Dynamic logic circcuits are much faster than static logic implementations and
References: [1] Synchronous Precharge Logic, by MAREK SMOSANZA. csail.mit.edu/6.371/handouts/L11.pdf 2002).MIT lectures. (10