Consistency Model
Memory Consistency Models1
David Mosberger
TR 93/11
Abstract
This paper discusses memory consistency models and their influence on software in the context of parallel machines. In the first part we review previous work on memory consistency models. The second part discusses the issues that arise due to weakening memory consistency. We are especially interested in the influence that weakened consistency models have on language, compiler, and runtime system design. We conclude that tighter interaction between those parts and the memory system might improve performance considerably. Department of Computer Science
The University of Arizona
Tucson, AZ 85721
1
This is an updated version of [Mos93]
1 Introduction
increases.
Shared memory can be implemented at the hardware or software level. In the latter case it is usually called
Distributed Shared Memory (DSM). At both levels work has been done to reap the benefits of weaker models. We conjecture that in the near future most parallel machines will be based on consistency models significantly weaker than SC [LLG+ 92, Sit92, BZ91, CBZ91, KCZ92].
The rest of this paper is organized as follows. In section 2 we discuss issues characteristic to memory consistency models. In the following section we present several consistency models and their implications on the programming model. We then take a look at implementation options in section 4. Finally, section 5 discusses the influence of weakened memory consistency models on software. In particular, we discuss the interactions between a weakened memory system and the software using it.
Traditionally, memory consistency models were of interest only to computer architects designing parallel machines. The goal was to present a model as close as possible to the model exhibited by sequential machines.
The model of choice was sequential consistency (SC).
Sequential consistency guarantees that the result of any execution of n processors is
David Mosberger
TR 93/11
Abstract
This paper discusses memory consistency models and their influence on software in the context of parallel machines. In the first part we review previous work on memory consistency models. The second part discusses the issues that arise due to weakening memory consistency. We are especially interested in the influence that weakened consistency models have on language, compiler, and runtime system design. We conclude that tighter interaction between those parts and the memory system might improve performance considerably. Department of Computer Science
The University of Arizona
Tucson, AZ 85721
1
This is an updated version of [Mos93]
1 Introduction
increases.
Shared memory can be implemented at the hardware or software level. In the latter case it is usually called
Distributed Shared Memory (DSM). At both levels work has been done to reap the benefits of weaker models. We conjecture that in the near future most parallel machines will be based on consistency models significantly weaker than SC [LLG+ 92, Sit92, BZ91, CBZ91, KCZ92].
The rest of this paper is organized as follows. In section 2 we discuss issues characteristic to memory consistency models. In the following section we present several consistency models and their implications on the programming model. We then take a look at implementation options in section 4. Finally, section 5 discusses the influence of weakened memory consistency models on software. In particular, we discuss the interactions between a weakened memory system and the software using it.
Traditionally, memory consistency models were of interest only to computer architects designing parallel machines. The goal was to present a model as close as possible to the model exhibited by sequential machines.
The model of choice was sequential consistency (SC).
Sequential consistency guarantees that the result of any execution of n processors is
References: GIT-CC-92/34, Georgia Institute of Technology, Atlanta, GA 30332-0280, USA, 1992. Leslie Lamport. Time, clocks, and the ordering of events in a distributed system. Communications of the ACM, 21(7):558–565, 1978. Parallel Processing, volume II, pages 252– 257, 1990. Addison-Wesley, Reading, Massachusetts, 1987.