advd
Exp. 2: finding relation between vgs and vds
Spice Code:
,,,,,,
\*** SPICE deck for cell NMOSCH1{sch} from library 2011A3PS271
*** Created on Thu Aug 22, 2013 14:45:24
*** Last revised on Thu Aug 22, 2013 15:13:10
*** Written on Thu Aug 22, 2013 15:13:17 by Electric VLSI Design System,
*version 9.04
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.global gnd
*** TOP LEVEL CELL: NMOSCH1{sch}
Mnmos-4@1 net@16 net@7 gnd gnd NMOS L=2U W=2U
VDS net@16 gnd DC 1V AC 0V 0
VGS net@7 gnd DC 1V AC 0V 0
* Spice Code nodes in cell cell 'NMOSCH1{sch}'
.include D:\ADVD\mos_models.txt
.dc VDS 0 5 0.1 VGS 0 5 0.1
Circuit:
.ENd
Observation:
It is seen that when the VGS is swiped VS VDS then the above output is seen.
As the VGS increases the ID also increases.
Exp. 2: finding relation between vgs and vds
Spice Code:
Q2) *** SPICE deck for cell pmos271{sch} from library 2011A3PS271
*** Created on Thu Aug 22, 2013 15:18:46
*** Last revised on Thu Aug 22, 2013 15:46:29
*** Written on Thu Aug 22, 2013 15:46:32 by Electric VLSI Design System,
*version 9.04
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.global gnd
*** WARNING: no power connection for P-transistor wells in cell
*'pmos271{sch}'
*** TOP LEVEL CELL: pmos271{sch}
Mpmos-4@1 net@19 net@7 gnd gnd PMOS L=2U W=2U
VDS gnd net@19 DC 0V AC 0V 0
VGC gnd net@7 DC 0V AC 0V 0
* Spice Code nodes in cell cell 'pmos271{sch}'
.include D:\ADVD\mos_models.txt
.dc VDS 0 5 0.1 VGC 0 5 .1
.END
Circuit:
Observation:
In PMOS the output of the similar swiping when applied then the magnitude if the ID will increase as the VGS is decreased to greater –ve value.
Exp. 2: finding relation between vgs and vds
Exp. 2: finding relation between vgs and vds
Spice Code:
Q3)
*** SPICE deck for cell PMOSQ2{sch} from library 2011A3PS271
*** Created on Thu Aug 22, 2013 15:50:37
*** Last
Spice Code:
,,,,,,
\*** SPICE deck for cell NMOSCH1{sch} from library 2011A3PS271
*** Created on Thu Aug 22, 2013 14:45:24
*** Last revised on Thu Aug 22, 2013 15:13:10
*** Written on Thu Aug 22, 2013 15:13:17 by Electric VLSI Design System,
*version 9.04
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.global gnd
*** TOP LEVEL CELL: NMOSCH1{sch}
Mnmos-4@1 net@16 net@7 gnd gnd NMOS L=2U W=2U
VDS net@16 gnd DC 1V AC 0V 0
VGS net@7 gnd DC 1V AC 0V 0
* Spice Code nodes in cell cell 'NMOSCH1{sch}'
.include D:\ADVD\mos_models.txt
.dc VDS 0 5 0.1 VGS 0 5 0.1
Circuit:
.ENd
Observation:
It is seen that when the VGS is swiped VS VDS then the above output is seen.
As the VGS increases the ID also increases.
Exp. 2: finding relation between vgs and vds
Spice Code:
Q2) *** SPICE deck for cell pmos271{sch} from library 2011A3PS271
*** Created on Thu Aug 22, 2013 15:18:46
*** Last revised on Thu Aug 22, 2013 15:46:29
*** Written on Thu Aug 22, 2013 15:46:32 by Electric VLSI Design System,
*version 9.04
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.global gnd
*** WARNING: no power connection for P-transistor wells in cell
*'pmos271{sch}'
*** TOP LEVEL CELL: pmos271{sch}
Mpmos-4@1 net@19 net@7 gnd gnd PMOS L=2U W=2U
VDS gnd net@19 DC 0V AC 0V 0
VGC gnd net@7 DC 0V AC 0V 0
* Spice Code nodes in cell cell 'pmos271{sch}'
.include D:\ADVD\mos_models.txt
.dc VDS 0 5 0.1 VGC 0 5 .1
.END
Circuit:
Observation:
In PMOS the output of the similar swiping when applied then the magnitude if the ID will increase as the VGS is decreased to greater –ve value.
Exp. 2: finding relation between vgs and vds
Exp. 2: finding relation between vgs and vds
Spice Code:
Q3)
*** SPICE deck for cell PMOSQ2{sch} from library 2011A3PS271
*** Created on Thu Aug 22, 2013 15:50:37
*** Last